	
	`timescale 1ns / 1ps
	module gtp_rx(
		input 	wire			clk 				,
		input 	wire 			rst 				,

		input	wire [0 : 31] 	m_axi_rx_tdata		,
		input	wire [0 : 3] 	m_axi_rx_tkeep		,
		input	wire 			m_axi_rx_tlast		,
		input	wire 			m_axi_rx_tvalid		,
		input	wire [0 : 31] 	m_axi_ufc_rx_tdata	,	
		input	wire [0 : 3] 	m_axi_ufc_rx_tkeep	,	
		input	wire 			m_axi_ufc_rx_tlast	,	
		input	wire 			m_axi_ufc_rx_tvalid	,

		output  wire 			error 
		);
	//==========================================
	//parameter define
	//==========================================
	parameter STREAM_LEN = 8192;


	reg 	[15:0]	cnt_burst 		;
	wire 			add_cnt_burst 	;
	wire 			end_cnt_burst 	;

	reg 			error_r 		;

	assign error  = error_r;


	always @(posedge clk) begin
		if (rst == 1'b1) begin
			cnt_burst <= 'd0;
		end
		else if (add_cnt_burst) begin
			if(end_cnt_burst)
				cnt_burst <= 'd0;
			else
				cnt_burst <= cnt_burst + 1'b1;
		end
	end

	assign add_cnt_burst = m_axi_rx_tvalid;
	assign end_cnt_burst = add_cnt_burst &&	cnt_burst == STREAM_LEN - 1;

	//----------------error_r------------------
	always @(posedge clk) begin
		if (rst==1'b1) begin
			error_r <= 1'b0;
		end
		else if (m_axi_rx_tvalid && (m_axi_rx_tdata != cnt_burst)) begin
			error_r <= 1'b1;
		end
	end
	/* wire [127:0]	probe0;
	assign probe0 = {
		m_axi_rx_tdata		,
		m_axi_rx_tkeep		,
		m_axi_rx_tlast		,
		m_axi_rx_tvalid		,
		m_axi_ufc_rx_tdata	,
		m_axi_ufc_rx_tkeep	,
		m_axi_ufc_rx_tlast	,
		m_axi_ufc_rx_tvalid	,
		error_r,
		cnt_burst
	};
	ila_0 inst_rx (
		.clk(clk), // input wire clk


		.probe0(probe0) // input wire [127:0] probe0
	); */
	
	
	
	
	
	// input	wire [0 : 31] 	m_axi_rx_tdata		,
		// input	wire [0 : 3] 	m_axi_rx_tkeep		,
		// input	wire 			m_axi_rx_tlast		,
		// input	wire 			m_axi_rx_tvalid		,
	
	
	
	ila_AURORA_RECEIVE ila_AURORA_RECEIVE (
	.clk(clk), // input wire clk


	.probe0(m_axi_rx_tdata), // input wire [31:0]  probe0  
	.probe1(m_axi_rx_tkeep), // input wire [3:0]  probe1 
	.probe2(m_axi_rx_tlast), // input wire [0:0]  probe2 
	.probe3(m_axi_rx_tvalid), // input wire [0:0]  probe3
	.probe4(error_r)
	);
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	endmodule